1. Field
The following description relates to delay-locked loop (DLL) locking. Also, the following description relates to a DLL circuit apparatus with improved DLL locking speed that performs a DLL locking operation within a shortened time, and a corresponding DLL locking method.
2. Description of Related Art
Ongoing efforts attempt to increase the processing speed of semiconductor memory devices while minimizing power consumption. These efforts attempt to address increasing demand for lower power consumption and faster processing by semiconductor memory devices. Because many semiconductor memory devices are portable devices that use a battery with limited energy supplies, the ability to provide lower power consumption extends the time such devices may be used, while faster processing improves the performance of the devices.
To help achieve lower power consumption and faster processing, the delay times of the internal circuits of the semiconductor memory devices may be compensated. To perform such compensation, input and output signals of the semiconductor memory device are synchronized with an external clock signal. To achieve this synchronization, the semiconductor memory device operating in synchronization with such a clock signal includes an internal clock generator such as a delay-locked loop (DLL) that receives an external clock signal and generates an appropriate internal clock signal.
That is, the DLL delays an external clock signal externally supplied to it, to generate an internal clock signal to drive a data output buffer. By doing so, output data is provided in response to the internal clock and in agreement with a rising edge or a falling edge of the external clock.
FIG. 1 is a circuit diagram of a DLL circuit.
Referring to FIG. 1, the DLL circuit 10 includes a phase frequency detector (PFD) 12 that compares a phase difference between an external clock signal (CLK) and a feedback internal clock signal (FB_CLK), and outputs a signal based on the result of the comparison. For example, the signal that results from the comparison is a rising edge pulse signal or falling edge pulse signal according to the relationship of the above two clock signals.
A charge pump (CP) 14 is provided to receive the rising or falling edge pulse signal as two input pulse signals from the PFD 12. The CP 14 converts these two pulse signals into voltage signals, extracts a DC component through a loop filter (not illustrated) and outputs a control signal voltage value (VCTRL) to vary the delay time.
A voltage controlled delay line (VCDL) 16 is provided so that when the control signal voltage value (VCTRL) is delivered, the VCDL 16 adjusts an external clock in accordance with the delay time and generates an internal clock signal. The clock signal of the VCDL 16, FB_CLK, is fed back to the PFD 12.
The DLL circuit 10 also includes a DLL initialization control unit 20 that initializes the DLL operation according to a detection result of a lock detector 18. The lock detector 18 detects whether the VCTRL is in a normal operation domain, which occurs when the DLL circuit 10 is normally driven. The DLL initialization control unit 20 initializes the PFD 12 and the CP 14 when the FB_CLK frequency is detected as deviating from the normal operation domain by the lock detector 18.
As explained above, the DLL circuit 10 continuously compares the internal feedback clock (FB_CLK) with the external clock (CLK). Based on the comparison, the DLL circuit 10 performs DLL locking while varying the VCTRL in accordance with the phase difference as determined by the comparison process. The ‘DLL locking’ as used herein refers to when the frequency and phase of the external clock (CLK) and internal clock (FB_CLK) are conformed to each other.
However, the control signal may sometimes take on an undesirable voltage value. For example, when the DLL circuit 10 of FIG. 1 is affected by an electrostatic discharge (ESD) or external noise generated by external effects, or the like, VCTRL varies and DLL locking has to be performed again. When the control signal takes on an undesirable voltage value, it takes a considerable amount of time to perform the DLL locking again. This issue is discussed further below.
FIG. 2 is a graph representing the relationship between the VCDL and the VCTRL that is the output from the CP, when external noise is applied.
When the DLL circuit 10 operates, with reference to FIG. 2A, the starting point, which is point A, moves to point B, so that DLL locking is performed. Point B is in the normal operation domain of the DLL circuit 10.
However, the VCTRL may sometimes deviate from the normal operation domain. For example, the deviation may occur due to influence of ESD or external noise, as discussed previously. That is, with references to FIG. 2B, point B may instantly move to point C due to such a deviation. In this case, the DLL circuit has to move VCTRL from point C back to point B for the purpose of DLL locking so that it will be back in the normal operation domain.
However, in such a situation, existing approaches take approximately several dozens of μs to move VCTRL back to the normal operation domain. Such time requirements are not very different from the initial DLL locking time that is done at the DLL circuit 10 at early stages of using the DLL circuit 10.
As a result, undesirable data appears on certain lines of the screen of the device using a DDI chip that uses such a DLL circuit 10.